In recent years, development has been actively made of a nonvolatile storage device which does not allow data stored therein to disappear even when an external power source is turned OFF. Reduction in cell area using Floating Gate (FG) type memory and thinning of an insulating film have been the main stream of FLASH memory miniaturization up to the 0.13-μm generation. With respect to the 90-nm generation and later, however, the thinning of an insulating film has become difficult from the viewpoint of data retention properties securing and, hence, attention has been paid to trap type memory utilizing traps in an insulating film serving as a charge accumulating layer.
The trap type memory has advantages over the FG type memory in that the trap type memory allows a reduction to be made in equivalent oxide film thickness including thinning of a tunnel oxide film and has a simpler device structure than the FG type memory. The trap type memory enables writing of two bits or more per cell to be realized by utilizing charge localization properties and hence is advantageous in reducing the cell area per bit.
FIGS. 25 and 26 are top views of related trap type memory, FIG. 26 includes sectional views of the related trap type memory taken on line I-I′ and line II-II′ of FIG. 25.
As shown in FIG. 25, in the trap type memory, isolation regions 8 are located in predetermined regions of a semiconductor substrate to define active regions including source/drain regions 5 and 6. A plurality of gate electrodes 1 extend across active regions 5,6, while charge accumulating layer 3 is formed between each gate electrode 1 and each active region 5, 6. Gate sidewall 16 and sidewall 17 are provided on each of opposite sides of gate electrode 1.
First insulating film 2, charge accumulating layer 3, second insulating film 4 and gate electrode 1 are sequentially provided on silicon substrate 7 shown, and gate sidewall 16 and sidewall 17 are provided on each of opposite sides of these layers. Source region 5 and drain region 6 are formed in the semiconductor substrate on opposite sides across gate electrode 1. At that time, first insulating film 2, charge accumulating layer 3 and second insulating film 4 have been removed in a manner self-aligned with gate electrode 1 and, hence, the charge accumulating layer is not formed outside gate electrode 1.
FIG. 27 illustrates a method for manufacturing trap type memory having the conventional structure shown as taken along line I-I′ of FIG. 26.
Initially, as shown in FIG. 27(a), a first insulating film 2 material, a charge accumulating layer 3 material, a second insulating film 4 material and gate electrode material 1 are sequentially stacked over an active region of silicon substrate 7. Thereafter, as shown in FIG. 27(b), gate electrode material 1 is patterned into a gate electrode shape by using a photolithography technique and a dry etching process. Further, exposed portions of the first insulating film 2 material, charge accumulating layer 3 material and second insulating film 4 material are removed by etching using gate electrode 1 thus patterned as a mask. Subsequently, as shown in FIG. 27(c), gate sidewall portion 16 is formed by conducting deposition of an insulating film and dry etch back. Subsequently, source region 5 and drain region 6 are formed and finally, sidewall 17 is formed as shown in FIG. 27(d) by conducting deposition of an insulating film and dry etch back.
In the manner described above, the trap type memory having the conventional structure can be manufactured.
Since the amount of charge in charge accumulating layer 3 can be controlled by a low gate voltage, a method including injecting hot carriers generated in substrate 7 and drain electrode 6 into charge accumulating layer 3 is used as writing and erasing operations of the trap type memory controlling the amount of charge in charge accumulating layer 3. FIG. 28 includes enlarged views illustrating a region around a drain edge. As shown in FIG. 28(a) the writing operation includes injecting hot electrons generated by application of positive voltage to gate conductive layer 1 and drain electrode 6 into charge accumulating layer 3. As shown in FIG. 28(b), the erasing operation includes causing interband tunneling to occur in a drain region overlapping the gate electrode by application of negative voltage to gate conductive layer 1 and positive voltage to drain electrode 6 and then injecting holes generated at that time into charge accumulating layer 3 by the negative voltage applied to gate conductive layer 1 while accelerating (making hot) the holes by the electric fields of drain electrode 6 and substrate 7, thereby neutralizing the holes with electrons in charge accumulating layer 3.
FIG. 28(c) shows a charge amount distribution of electrons injected into the charge accumulating layer by hot electron injection. Distribution 11 has a horizontal scale matching the horizontal scale of the charge accumulating layer. A problem with the conventional structure resides in that some of the injected electrons go out of a charge accumulating region comprising insulating film 3 and hence escape into gate sidewall portion 16, sidewall 17 and the substrate as depicted by the broken line in distribution II without being accumulated in charge accumulating layer 3.
For this reason, the writing efficiency of injected charge lowers, so that the writing time increases. In this case, the whole of distribution 11 can be made to fall within the charge accumulating layer by expanding drain region 6 up to a central portion of a channel (toward the side immediately below the gate electrode), thereby making it possible to enhance the writing efficiency. With drain region 6 thus configured, however, an increase in floating capacitance is caused to occur by expansion of the portion of drain region 6 overlapping gate electrode 1, thereby lowering the operation speed.
With the manufacturing method for the conventional structure, in the etching process of second insulating film 4, charge accumulating layer 3 and first insulating film 2 as shown in FIG. 27(b), defects occur at edge portions of these insulating films after etching. Since such detects remain at the edge portions of the insulating films even after the formation of gate sidewall 16, an increase in leakage current and leakage of accumulated charge occur through the defects, thus causing the yield to lower.
In this case, if the gate sidewall portion is formed by thermal oxidation, the edge portions of insulating films 2, 3 and 4 are oxidized at the same time therewith, so that restoration from some of the defects are made. However, since bird's beaks are formed at the edge portions of the insulating films by the thermal oxidation, the defect density grows in the edge portions of the first insulating film, thus lowering the yield on the contrary.
To obviate the problems associated with the above-described conventional structure, Japanese Patent Laid-Open No. 2003-60096 discloses a structure in which charge accumulating layer 3 protrudes from gate electrode 1. FIG. 29 is a top view of trap type memory having the second conventional structure described in Japanese Patent Laid-Open No. 2003-60096, and FIG. 30 includes sectional views of the trap type memory having the second conventional structure taken along line I-I′ and line II-II′ of FIG. 29. In the case of this trap type memory, first insulating film 2, charge accumulating layer 3 and second insulating film 4 protrude to extend under sidewall 17, as shown in FIG. 29 and in the I-I′ sectional view of FIG. 30.
A method for manufacturing the trap type memory having the second conventional structure will be described with reference to FIG. 31 including sectional views taken along line I-I′ of FIG. 30.
Initially, as shown in FIG. 31(a), a first insulating film 2 material, a charge accumulating layer 3 material, a second insulating film 4 material and a gate electrode 1 material are sequentially stacked over an active region of silicon substrate 7. Subsequently, as shown in FIG. 31(b), the gate electrode 1 material is patterned into a gate electrode shape by using a photolithography technique and a dry etching process, and etching in the patterning is stopped at second insulating film 4. Thereafter, as shown in FIG. 31(c), gate sidewall 16 is formed by conducting deposition of an insulating film and dry etch back. Further, ion implantation through insulating films 2, 3 and 4 is conducted using the gate electrode as a mask to form source region 5 and drain region 6. Subsequently, as shown in FIG. 31(d), sidewall 17 is formed by conducting deposition of an insulating film and dry etch back. Finally, exposed portions of the second insulating film 4 material, charge accumulating layer 3 material and first insulating film 2 material are removed by etching using the gate electrode and the sidewall as a mask, thus giving the second trap type memory.